Electronics devices are developing towards more compact form factors, more versatility, higher performance, and lower power consumption, driving IC packaging technologies towards SiP (System-in-Package) from single chip package. Among various SiP technologies, TSV 3D IC (Through-Silicon-Via) which vertically interconnects stacked dies using TSV technology has been considered the future packaging technology due to its high space efficiency and performance.
Up to now, TSV 3D IC technology has only been applied to the integration of homogeneous chips, resulting in a low industrial value. However, the situation is about to change as some foreign vendors are projected to make technological progress. This report provides the overview development of TSV 3D IC from the aspects of technology, market, and industry.